SPS 2019 old

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International Semiconductor Panel Symposium (SPS) 2019


December 17 & 18, 2019
Nanhai Jiayia International Hotel
Foshan China
No.55 Middle Bo'ai Road (Bo'ai Zhong Lu),
Shishan Town Nanhai District Foshan
528225 China

Short Courses

  • Tuesday December 17 - 9:00 - 13:00
Optional short courses requires additional registration
(lunch included)

 
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From Wafer to Panel Level Packaging

Tanja Braun
Fraunhofer IZM Berlin

 
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Stress Analysis and Reliability Management in Advanced Packaging

Xuejun Fan
IEEE Distinguished Lecturer

Technical Presentations

  • Tuesday December 17 - 13:00 - 17:30
  • Wednesday December 18 - 8:00 - 15:00
Confirmed Presenters Include

13:00 - 15:00

Session 1
Introduction, Keynote, & Market Overview


 
 

Opening Remarks

Tingyu Lin & Ira Feldman


 
 

Formal Welcome

Yang Haidong
GGDCNC


 
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Keynote

Johan Liu
The Royal Swedish Academy of Sciences


 
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Market Overview

Santosh Kumar
Yole

Santosh Kumar is currently working as Director & Principal Analyst at Yole Développement. He is involved in the market, technology and strategic analysis of the microelectronic assembly and packaging technologies. His main interest areas are advanced IC packaging technology including equipment & materials. He is the author of several reports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging.

He received the bachelor and master degree in engineering from the Indian Institute of Technology (IIT), Roorkee and University of Seoul respectively. He has published more than 40 papers in peer reviewed journals and has obtained 2 patents. He has presented and given talks at numerous conferences and technical symposiums related to advanced microelectronics packaging.


15:30 - 17:30

Session 2
Industry Status, IDM/Fabless Perspective


 
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High Frequency Power Converters with 3D Package-embedded Inductors

Dr. Ziyang Gao
ASTRI


Dr. Ziyang GAO is a Director of the 3D Integration CCG of the Integrated Circuits and Systems (ICS) Technology Division in ASTRI. He received his B.S. Degree from the University of Science & Technology of China (USTC) and his Ph.D Degree from the Hong Kong University of Science and Technology (HKUST). He had worked at the Chinese Academy of Sciences (CAS), HKUST, and joined ASTRI in 2006.

Currently he is leading the 3DI CCG to develop power electronics solutions by leveraging 3D integration technologies for telecommunication, data centers and other power conversion applications. He also serves as the technical committee member of the International Conference on Electronic Packaging Technology (ICEPT) and the International Technology Roadmap for Wide-bandgap Semiconductors (ITRW). He published 28 peer-reviewed international journal & conference papers and filed 34 US and CN patent applications with three of them awarded two Gold medals and one Silver medal in the 46th & 47th International Exhibition of Innovations in Geneva.

 
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Challenge on Electronic Packaging

Tonglong Zhang / 张童龙
HiSilicon

 
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Fan Out Development and Solutions

Thorsten Meyer
Infineon

17:30 - 18:30

Networking Reception in EXPO area


 

Adjourn


8:30 - 10:00

Session 3
OSAT & Packaging Technology


 
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Development of eSiFO Gat Huatian

Dr. Yu Daquan
Infineon

10:30 - 12:00

Session 4
Materials


 
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Total Solution for Fan Out Panel Level Packaging

Toshihisa Nonaka
Hitachi Chemicals

13:00 - 15:00

Session 5
Equipment & Processes


 
 

Development of TBDB

Wang Huilian/王汇联
Xiamen(China)Semiconductor Investment Group Co., Ltd.


15:00 - 16:00

Networking Tea Break in EXPO area


 

Adjourn



Program subject to change without notice

For additional information please contact sps2019@testconx.org