SPS 2019

Panel Level Packaging (PLP) is one of the latest trends in microelectronics packing. Besides technology developments towards heterogeneous integration including multiple die packaging, passive component integration in package and redistribution layer or package-on-package approaches also larger substrates formats are targeted. Manufacturing is currently done on wafer level up to 12”/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, PLP might be the next big step. PLP has the opportunity to adapt processes, materials and equipment from other technology areas. Printed Circuit Board (PCB), Liquid Crystal Display (LCD) or solar equipment is manufactured on panel sizes and offer new approaches also for PLP. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. The PDC will give a status of the current Fan-in and Fan-out Wafer Level Packaging as well as Panel Level Packaging including Fan-out Panel Level Packaging and Substrate Embedding approaches. This will include material discussion, technologies, applications and market trends.

Tanja Braun studied mechanical engineering at Technical University of Berlin with a focus on polymers and micro systems and joined Fraunhofer IZM in 1999. Since 2000 she is working with the group Assembly & Encapsulation Technologies and since 2016 she is head of this group. In 2013 she received her Ph.D. degree from the Technical University of Berlin for the work focusing on humidity diffusion through particle-filled epoxy resins. Her field of research is process development of assembly and encapsulation processes, the qualification of these processes using both non-destructive and destructive tools and advanced polymer analysis. Recent research is focused on wafer and panel level packaging technologies and Tanja Braun is leading the Fan-out Panel Level Packaging Consortium at Fraunhofer IZM Berlin.

Tanja Braun 在柏林技术大学学习机械工程，专注于聚合物和微系统，并于1999年加入Fraunhofer IZM。自2000年以来，她一直与组装和封装技术集团合作，并自2016年起担任该集团的负责人。2013年，她获得了柏林技术大学的博士学位，主攻通过颗粒填充环氧树脂进行湿度扩散。她的研究领域是组装和封装工艺的工艺开发，使用无损和破坏性工具以及先进的聚合物分析对这些工艺进行鉴定。最近的研究集中在晶圆和面板级封装技术上，Tanja Braun领导着柏林Fraunhofer Izm的扇出面板级封装联盟。

10:40

Networking Tea Break

11:00

Stress Analysis and Reliability Management in Advanced Packaging
先进封装中应力分析及可靠性管理

Xuejun Fan
IEEE Distinguished Lecturer

In this short course, we will discuss two important reliability issues in advanced packaging: warpage control and solder joint reliability.

For warpage control, a novel method is presented to achieve zero-warpage for large-die/large package. A capped-die flip chip package is introduced, in which a metal cap tightly covers on the die and bonds with the die through an adhesive material. As a result, the capped die has a higher effective coefficient of thermal expansion (CTE). By adjusting the thickness of the metal cap, the effective CTE of the capped die can match with the CTE of the substrate. Theoretically, the warpage of the flip chip package can be reduced to an ultra low level, even zero warpage. In the meantime, the stress level inside the package is also reduced greatly. The key manufacture process step to make the capped die flip chip package is to concurrently cure the adhesive material for bonding the die cap with the die and the underfill material for filling the gap between the die the substrate. When the adhesive material that has the same or similar Tg as the Tg of the underfill material, warpage can be controlled to the minimum level. Shadow Moiré is used to measure the warpage from room to high temperature (260C). Experimental data show that in the temperature range from 25C to 260C, the warpage curve of the capped die package is almost flat, confirming the concept of the capped die flip chip package.

For solder joint reliability, a variety of wafer level packaging (WLP) structures, including both fan-in and fan-out WLPs, are introduced first from a structural design point of view. The effects of redistribution layer (RDL), bump structural design/material selection, polymer-cored ball application, and PCB design/material selection are illustrated. We will focus on several different WLP technologies, such as ball on I/O, ball on polymer, and copper post WLP. It will be shown that a compliant layer between silicon and solder balls creates a ‘cushion’ effect to reduce the stresses in solder joints significantly. Such cushion effect can be achieved either by an extremely compliant film or a ‘hard’ film with a large coefficient of thermal expansion. We will also discuss the polymer-cored solder ball applications to enhance the reliability of solder joints. Both experimental and finite element analysis have demonstrated that making corner balls non-electrically connected can greatly improve the WLP thermomechanical reliability.

Xuejun Fan is a Regents’ Professor of Texas State University System, and a Mary Ann and Lawrence E. Faust Endowed Professor at Lamar University, Beaumont, Texas. Dr. Fan is an IEEE Fellow, and an IEEE Distinguished Lecturer. He currently serves as a member-at-large of the IEEE Electronic Packaging Society (EPS) Board of Governors. Dr. Fan gained significant experience in the microelectronics industry between 1997 and 2007, at IME, Philips and Intel. His current areas of expertise include characterization, modeling and reliability of materials, components, and systems in micro- and opto-electronics manufacturing and packaging. He received the Outstanding Sustained Technical Contribution Award in 2017, and Exceptional Technical Achievement Award in 2011, from the IEEE Electronic Packaging Society. In his early academia career in China, Dr. Fan was the recipient of a Young Faculty Award from the Fok Ying-Tung Education Foundation in 1994, and the nominee for the title of “Ten Outstanding Youth of China” in 1991. He was one of the youngest full professors in China at the age of 27 at Taiyuan University of Technology in 1991.

樊学军是德州州立大学的杰出教授，也是德州博蒙特拉马尔大学的玛丽·安学院和劳伦斯·E·浮士德学院的客座教授。范博士是电气和电子工程师协会（IEEE)研究员，IEEE杰出讲师。他目前是IEEE电子封装协会（EPS）理事会的成员。
樊博士在1997年至2007年间，先后就职于IME、飞利浦和英特尔，获得了微电子行业丰富从业经验。他目前专注于：微电子和光电子学制造和封装领域的特性描述、建模、材料可靠性验证、零部件和系统的整合等。
他在2017年获得了IEEE电子封装协会颁发的杰出持续技术贡献奖，并在2011年获得了杰出技术成就奖。樊学军教授在中国的早期学术生涯中，曾获1994年度霍英东教育基金会青年教师奖，1991年度“十大杰出青年”称号被提名人之一。1991年，27岁的他是太原科技大学中国最年轻的正教授之一。

12:00

Lunch and Networking

For paid short course atttendees and presenters.

13:30

Keynote

Keynote: Challenge on New Materials of Electronic Packaging

Johan Liu
Royal Swedish Academy of Sciences

Johan Liu，male，he received a master’s degree in 1984 and a doctorate in 1989 from KTH Royal Institute of Technology in Sweden.He is a chair professor of Chalmers University of Technology in Sweden, IEEE Fellow, academician of The Royal Swedish Academy of Sciences.

He has been selected as a special professor of the Yangtze River Scholars Program (short-term) and the National Thousand-Person Program (short-term), distinguished Professor of Shanghai University.

Deputy Editor of the International Journal of IEEE CPMT Transactions, one of the editorial board of the Journal Soldering & Surface Mount Technology and Journal Advance in Manufacture.Chief Scientist of Opel and Shenzhen Shenruimene.

He committed to nano-electronic materials and micro-nano manufacturing technology, especially heat dissipation materials, nano-electronic packaging technology and other research directions.

He Published 550 papers and chapters, including 80 papers in top journals such as Nature Communications, Advanced Materials, Advanced Functional Materials, Advanced Energy Materials, Small.citation times: 6400. H-index: 41. He has nearly 30 invention patents and 60 patent applications.

In 2004, he was awarded the Special Technology Achievement Award by the Devices and Packaging Branch of the American College of Electrical and Electronic Engineers (only one person per year).In 1996, he was awarded the Best Paper Award in Advanced Packaging Field by the American Journal of IEEE CPMT (only one person per year). He was co-chairman of China Electronic Packaging Conference from 2009 to 2018.

刘建影院士/Johan Liu（中英文对照）

刘建影，男，1984年获瑞典皇家理工学院硕士学位,1989年瑞典皇家理工学院获博士学位。现任瑞典查尔姆斯理工大学微系统和纳米科学学院讲座教授，IEEE Fellow，瑞典皇家工程科学院院士，入选“长江学者特聘教授”计划（短期）及国家“千人计划”（短期）, 上海大学特聘教授。

IEEE CPMT Transactions国际期刊副主编，Soldering & Surface Mount Technology期刊及Advance in　Manufacture杂志编委，欧泊及深圳深瑞墨烯首席科学家。

长期致力于纳米电子材料与微纳制造工艺的研究，特别是散热材料，纳米电子封装技术等方向的研究。发表550篇论文及章节，其中在Nature Communications, Advanced Materials、Advanced Functional Materials、Advanced Energy Materials, Small等顶级期刊上发表论文80篇，引用次数:6400。H-指数: 41。拥有近30项发明专利及60项专利申请。2004年获得美国电气电子工程师学院器件和封装分会“特殊技术成就奖” (每年只有一人获得)。1996年获得美国IEEE CPMT学报先进封装领域“最佳论文奖”，(每年只有一人获得)，2009至2018年中国电子封装大会共同主席。

Introduction of Guangdong Semiconductor Intelligent Equipment and System Integration Innovation Center (FZX)

Dr. Cui Chengqiang
Guangdong Semiconductor Intelligent Equipment and System Integration Innovation Center (FZX)

15:00

Tea Break

15:20

Session 1

SEMI Standards: Update on Panel Level Packaging Standardization

Isadora Jin
SEMI

A number of different formats – including circular and rectangular – have been proposed for the panels into which the die are embedded, with a large number of different rectangular sizes. This wide range is delaying broad acceptance of Panel Level Packaging (PLP) technologies, as the tools must be customized for each different format.
Panel substrates today range from 300 mm to 920 mm. Cost advantages depend on package and substrate size, and lack of standardization is a barrier to high volume manufacturing.

Despite its advantages, PLP has challenges to overcome. To address these issues, the SEMI Standards Panel Level Packaging Panel Task Force is currently developing standards focusing on panels, targeting dimensions, ID marking and orientation, edge exclusion, and other parameters such as total thickness variation (TTV), bow, and warp.

Biography:
Isa Dora Jin

Senior specialist of SEMI International Standards.
Takes charge of SEMI China Standards Committees (PV Technical Committee, PV Materials Technical Committee, HB-LED Technical Committee, Compound Semiconductor Technical Committee, etc).

High Frequency Power Converters with 3D Package-embedded Inductors

Dr. Ziyang GAO
Hong Kong Science and Technology Research Institute (ASTRI)

Dr. Ziyang GAO is a Director of the 3D Integration CCG of the Integrated Circuits and Systems (ICS) Technology Division in ASTRI. He received his B.S. Degree from the University of Science & Technology of China (USTC) and his Ph.D Degree from the Hong Kong University of Science and Technology (HKUST). He had worked at the Chinese Academy of Sciences (CAS), HKUST, and joined ASTRI in 2006.

Currently he is leading the 3DI CCG to develop power electronics solutions by leveraging 3D integration technologies for telecommunication, data centers and other power conversion applications. He also serves as the technical committee member of the International Conference on Electronic Packaging Technology (ICEPT) and the International Technology Roadmap for Wide-bandgap Semiconductors (ITRW). He published 28 peer-reviewed international journal & conference papers and filed 34 US and CN patent applications with three of them awarded two Gold medals and one Silver medal in the 46th & 47th International Exhibition of Innovations in Geneva.

Challenge on Electronic Packaging

Tonglong Zhang / 张童龙
HUAWEI- HiSilicon

Tonglong Zhang has more than 20 years’ experience in IC packaging development. He worked in a world top design house for 10 years and two OSATs for a total of 10 years. In addition, he worked in IDM for more than 3 years. He built up Cu pillar flipchip capability from zero to HVM within 1.5 years. He developed various new package technologies. He is also experienced in IC package design, FEA stress and thermal analysis. He have 11 US patents and more than 10 Chinese patents.

张童龙拥有20多年的集成电路封装开发经验。他在一家世界顶级设计公司OEM工作了10年，在两个OSAT公司工作了10年。此外，他在 IDM领域工作了3年多。他在1.5年内将铜柱倒装芯片的能力从零提高到HVM级别。他开发了各种新的封装技术。他在集成电路封装设计，有限元应力和热分析方面也很有经验。他拥有11项美国专利和10多项中国专利。

Recent Endeavors on WLP/PLP

Dr. Thorsten Meyer
Infineon

Thorsten Meyer is Lead Principal Engineer Package Concept Engineering at Infineon Technologies in Regensburg, Germany, responsible for New Package concepts. Until March 2015 he was leading the Package Technology and Innovation department at Intel Mobile Communications (IMC) in Regensburg. Prior joining IMC,
he was overall project leader for the development of Wafer Level Packaging Technologies at Infineon in Regensburg and earlier in Dresden.

Thorsten is author of multiple publications and holds more than 150 patents and patent applications in the area of advanced packaging.

Thorsten Meyer是英飞凌科技公司（位于德国雷根斯堡）的首席封装理念工程师，，负责研发新的封装理念。直到2015年3月，他一直领导着英特尔移动通信（IMC）（位于德国雷根斯堡）的软件封装技术与创新部门。在加入IMC之前，他曾在英飞凌公司和德累斯顿公司担任晶圆级封装技术开发的总体项目负责人。Thorsten Meyer是多个出版物的作者，在先进封装领域拥有150多项专利和专利申请。

Wet Coating Technique for Panel Level Package

Koichi Jono
SCREEN, Finetech Solutions Co., Ltd.

Abstract : Recently, development of cost-superior Fun-out PLP over WLP is actively underway.
In package process for panel level, several customers have been consider about using functional liquid materials.

Biography:I will introduce the problem and the counter measure for coating technique of various materials.I got master’s degree in materials engineering from Kyoto Institute of Technology in March 2000.

I joined DaiNippon SCREEN Mfg Co., Ltd. (currently SCREEN HD) in April 2000.
At first, I belonged to the R&D department and involved in commercialization of the FM series cleaning equipment for LCD panels.
From the end of 2001, I was in charge of developing slit coaters for liquid resists, and commercialized as Linearcoater®.
At the peak of LCD TVs products, I had been responsible for the process at the user site for 10 years.
In 2012, I was involved in the development of slit coating equipment for packages.
(LC-M series which is coating machine for package was released in 2014)
Since then, I have been in charge of developing equipment that can handle various substrates and chemicals.

18:00

Networking Reception

For all attendees

Wednesday December 18, 2019

8:00

Registration Opens

8:30

Session 2

Development of eSiFO Gat Huatian

Dr. Yu Daquan
HuaTian Scientific Co

Dr. Yu Daquan gained the doctorate and graduated from Dalian University of Technology in 2004.
He has successively carried out scientific research at City University of Hong Kong, German Institute of Micro-integration and Reliability, and Singapore Institute of Microelectronics.
In 2010, he returned to China as a researcher of Institute of Microelectronics, Chinese Academy of Sciences.After that ,He servedTianshui Huatian Technology Group as the CTO as well as the dean of the Institute of Packaging Technology.

He was the general manager of Xiamen Yuntian Semiconductor Technology Co., Ltd.

Minjiang Scholar of Xiamen University selected him as a distinguished professor in December 2018.

Dr. Yu Daquan has been engaged in the research and industrialization of advanced microelectronic packaging technology for many years.

He has published more than 170 academic papers and authorized more than 50 invention patents. Dr. Yu Daquan is a senior member of IEEE.

He has been selected as the leader of “Double Creative Talents” and “Double Creative Team” in Jiangsu Province (2016).

于大全（中英文对照）

博士，2004年博士毕业于大连理工大学。先后在香港城市大学、德国夫豪恩霍夫微集成与可靠性研究所、新加坡微电子研究所开展科研工作。
2010年回国后先后担任中国科学院微电子研究所研究员，天水华天科技集团CTO、封装技术研究院院长，厦门云天半导体科技有限公司总经理，2018年12月入选厦门大学闽江学者特聘教授。于大全博士多年来一直从事先进微电子封装技术研究与产业化工作，发表学术论文170多篇，授权发明专利50多项。于大全博士是IEEE高级会员，曾入选江苏省“双创人才”和“双创团队”领军人才（2016）。

Advanced Material Development

Toshihisa Nonaka
Hitachi Chemicals

Results of both of chip first and last panel level packaging development including material and process will be presented. And the activity was carried out at packaging solution center of Hitachi Chemical and some of them were co-worked with collaborator of “JOINT” consortium members. The consortium is also introduced.

He graduated from the University of Tokyo in 1986 and received Ph. D degree in 1995 from Nagoya University. He has been working in the research of electronic materials more than 30 years. From 1986-2015 he had been worked in Toray industries. Since 2015 he has been a technical director of Packaging Solution Center of Hitachi Chemical.
Current his research topic is process and material development of advance package regarding FO-WLP/PLP, 2.5D, 3D and so on.

High Performance Base Materials for IC Substrate & Packaging

Yang Zhongqiang
SYTECH

Yang zhongqiang ,Male,qiyang city,Hunan province，Master of engineering, senior engineer of polymer materials (professor level).
Currently，he is the director of the National Electronic Circuit Substrate Engineering Technology and Research Center.

He has been engaged in the technical research ,development and the management of printing the circuit boards with the technology of electronic circuit substrating the copper clad plate.for a long time.

He is mainly responsible for the research and development of new technologies and new products of SYSTECH CO.,LTD.

He undertaked and participated many national and provincial projects related to his research area. He has won a second prize both in National Technical Invention and in Guangdong Science and Technology Award.

杨中强，男，湖南祁阳人，工学硕士，高分子材料高级工程师（教授级）。现在广东生益科技股份有限公司任职国家电子电路基材工程技术研究中心主任，长期从事印制电路板用电子电路基材覆铜板的技术研发和研发管理工作，主要负责新技术、新产品的研究开发；承担和参与完成国家级、省部级项目多项；曾获国家技术发明二等奖一项，广东省科学技术奖二等奖一项。

Materials - to be announced

Dr Yuan Mingjun
GUANGHUA TECHNOLOGY

10:30

Tea Break

10:45

Session 3

PLP Development in World Wide

Santosh Kumar
Yole Development

Santosh Kumar is currently working as Director & Principal Analyst at Yole Développement. He is involved in the market, technology and strategic analysis of the microelectronic assembly and packaging technologies. His main interest areas are advanced IC packaging technology including equipment & materials. He is the author of several reports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging.

He received the bachelor and master degree in engineering from the Indian Institute of Technology (IIT), Roorkee and University of Seoul respectively. He has published more than 40 papers in peer reviewed journals and has obtained 2 patents. He has presented and given talks at numerous conferences and technical symposiums related to advanced microelectronics packaging.

Abstract - Biography (English)

Santosh Kumar目前在Yole development pement担任董事兼首席分析师。他主要从事微电子组装和封装技术的市场、技术和战略分析。他的主要研究领域是先进的集成电路封装技术，包括设备和材料，撰写了多篇关于扇出/扇入WLP、倒装芯片和3D/2.5D封装的报告。

他分别在印度理工学院(IIT)、罗基大学(Roorkee)和首尔大学(University of Seoul)获得工程学学士和硕士学位。在同行评审期刊上发表论文40余篇，获得专利2项。曾在许多与先进微电子封装有关的会议和技术研讨会上发言。

Applications of Micro-Analysis in the
Electronics Industry for Failure Analysis -
From Material to Device

Lin Nan
EDAX

Failure analysis has been always an important topic in semiconductor and electronics which assures device R&D process and device reliability . EDAX, as the top scientific equipment manufacture for material analysis, and as the inventor and pioneer for both EDS and EBSD technology, its equipment and technology has proven to be a mature, effective and reliable method, which has been widely used for detects, impurities and material distribution and microstructure studies.

As the semiconductor device scales down, the failure analysis become more and more important because not only the material composition and distribution but also its microstructure is deciding the device performance.

EBSD as a recent developed technology in 1990s’, resolves the difficulties for microstructure analysis, especially for the IMCs in semiconductors and more become more and more popular.

The applications in this presentation for EDS maybe an old story but some of the examples showed in EBSD may give you a fresh idea about the device microstructures. A combination of both will definitely provide a more in-depth, accurate and effective method for the device/material failure analysis and facilitate the whole industry to move forward.

Graduated with Bachelor of Science in Physics with Honors from National University of Singapore and continued with his Master of Science in Management of Technology, National University of Singapore.

He has spent 4 years graduation in the semiconductor industry in GlobalFoundries Singapore after then join Gatan Inc, and started his career in the Electron microscope mciro-analysis industry as a sales manager.

He currently worked as country manager of China including Taiwan in EDAX, part of Ametek one of the top scientific companies in the world with 5 billions revenue.

摘要 - 简介 (Chinese)

失效分析一直都是半导体行业中工艺研发和产品可靠性的重要保证。作为全球顶尖的微结构软硬件供应商，EDAX公司首创EDS和EBSD分析技术，这两种技术均被证明是成熟有效且高度可靠的方法，现已被广泛应用于检测、杂质和材料分布以及微结构研究等领域。

随着半导体设备规模的缩小，失效分析变得越来越重要，设备的性能不仅取决于材料的组成和分布，还取决于微结构。EBSD技术是20世纪90年代发展起来的一项新技术，它解决了微结构分析的难题，尤其是半导体材料中的imcs，因此越来越受到人们的青睐。本次演讲中对于EDS技术的应用也许是老生常谈，但在讲到EBSD技术时展示的一些示例一定会让您对设备的微结构有新的灵感。

总而言之，EBSD和EDS两者的结合必将为设备或材料的失效分析提供更深入、准确和有效的方法，从而促进整个半导体行业的发展。

林楠，以优异的成绩毕业于新加坡国立大学物理系，获得理学学士学位。随后继续攻读该校硕士，并获得产业技术管理硕士学位。在毕业后的4年时间里，他一直在新加坡的Globalfoundires公司从事半导体行业。随后加入Gatan Inc，以销售经理的身份开启了他在电子显微镜分析行业的职业生涯。目前，他在Amete的子公司EDAX担任大中华区经理，该公司是全球顶尖的科技公司之一，年收入高达50亿美元。

Exploring the Regional Semiconductor Industry Ecology in Post-Moore Era

Wang Huilian/王汇联
Xiamen Semiconductor Investment Group Co., Ltd

Successively served as assistant director and director of industrialization department of institute of microelectronics, Chinese academy of sciences, deputy director of iot research and development center, Chinese academy of sciences. Led and participated in the investment (merger and acquisition) and management of nearly 100 semiconductor enterprises, and worked in semiconductor industry for more than 20 years, with strong experience in resource integration and industry.

Abstract - Biography (English)

王汇联(wang huilian)，现任厦门半导体投资集团公司董事总经理。在半导体学术界、工业界工作超过20多年，曾在国家集成电路设计深圳产业产业化基地、中国科学院深圳先进技术研究院、中国科学院微电子所和中国科学院物联网研究发展中心等单位任职。半导半导体业的多年从业经验，对半导体产业和信息技术产业理解深刻，曾经主导（参与）的技术转移转化、投资（并购）项目近百项，对产业发展方向、驱动市场具有较强的洞察力。

12:00

Lunch and Networking

13:35

Session 4

FOPLP Solution for Cu
RDL Formation

Dr. Richard Tsai

MANZ

Fan-out panel level packaging (FOPLP) is a highly promising new approach in the advanced packaging field due to its advantage of higher productivity and lower production cost comparing to that of fan-out wafer level packaging (FOWLP). Manz has more than 30 years of successful production experience in self-development with
8,000 sales record of PCB and FPD production equipment. With the integration of diverse core technologies, strong independent R&D strength, and the integration of cross-field equipment, Manz has been demonstrating the capability of providing innovative and cost-effective solutions to customers with a series of customized wet
bench equipment, such as cleaner, coater, developer, etcher, stripper, electrochemical plating tools and automation to meet customers’ requirements for high quality production of FOPLP.

The development of wet bench equipment for advanced packaging technology is one of the major R&D projects in Manz group aiming to integrate Manz’s fruitful knowledge of PCB and FPD technologies to the potential and promising new market.
Dr. Richard Tsai has assigned to be one of the leaders to manage the development of the novel wet bench equipment for advanced packaging field.

He has worked in advanced packaging field since 2009 and used to be the technical manager in TSMC who won “TSMC R&D Idea Forum Award”. Moreover, filed some important patents. With the practical research and technology expertise of the process flow of 3D IC packaging development in IC industry, he is currently focusing on the Manz wet
bench equipment optimization and core technologies synchronization in order to implement into advanced packaging market.

摘要 - 简介 (Chinese)

演講摘要 Abstract:
扇出型面板级封装在先进封装领域中是一全新发展的技术。相较于扇出型晶圆级封
装，扇出型面板级封装具有较高的生产效率及较低的生产成本。亚智科技有超过 30
年的成功生产经验，在 FPD 及 PCB 产业有超过 8000 台设备销售实绩。藉由整合
集团内多元核心技术、强大独立研发能量、及整合跨领域设备，亚智科技一直展现具
有提供创新及价格优势的生产解决方案，诸如：清洗机、涂布机、显影机、蚀刻机、
剥膜机、电镀机及自动化设备，目前已成功开发并应用于扇出型面板级封装之高质量
生产需求。

蔡承佑博士目前为 Manz 亚智科技先进封装技术研究及发展计划人之一，负责统筹集
团内湿法制程技术开发，以应用于新兴先进封装技术。此计划为近年来集团内研究及
开发重大项目之一，旨在活化集团内显示器及印刷电路板之技术，同时进一步提升研
发能量，应用于未来具有发展潜力的新兴技术。

2009 年即开始投入先进封装之相关研发工作的蔡承佑博士，在加入 Manz 亚智科技前
任职于台湾集成电路制造股份有限公司担任技术副理，任职期间曾获＂TSMC R&D
Idea Forum Award＂，并发表数篇重要专利。熟悉 3D IC 先进封装关键工艺流程的专
业知识、集成电路产业链的发展，目前正与团队进行进一步的开发与研究，构思更高
性能的设备及解决方案，目标再次提升 Manz 在先进封装市场的竞争力。毕业于台湾
国立中央大学物理系博士。

PLP Development

Farhang Yazdani

BroadPak

Farhang Yazdani is the President and CEO of BroadPak Corporation. BroadPak is internationally recognized as the “key provider of innovative total solution for 2.5D/3D products”. Through his 20 years with the industry, he has served in various technical, management, and advisory positions with leading semiconductor companies worldwide. He is the author of the book “Foundations of Heterogeneous Integration: An Industry-Based, 2.5D/3D Pathfinding and Co-Design Approach”. He is the recipient of 2013 NIPSIA award in recognition of his contribution to the advancement and innovations in packaging technologies. He has numerous publications and IPs in the area of 2.5D/3D Packaging and Assembly, serves on various technical committees and is a frequent reviewer for IEEE Journal of Advanced Packaging. He received his undergraduate and graduate degrees in Chemical Engineering and Mechanical Engineering from the University of Washington, Seattle.

Farhang Yazdani是BroadPak Corporation的总裁兼首席执行官。 BroadPak是国际公认的“2.5D / 3D产品创新整体解决方案的主要提供商”。他在该行业工作了20年，他曾在全球领先的半导体公司担任过各种技术，管理和咨询职位。他是“异构整合的基础：一个行业基础，2.5D / 3D寻路和协同设计方法”一书的作者。他是2013年NIPSIA奖的获得者，以表彰他对包装技术的进步和创新所做出的贡献。他在2.5D / 3D包装和装配领域拥有众多出版物和知识产权，在各种技术委员会任职，并且是IEEE Journal of Advanced Packaging的常用评论员。他获得了西雅图华盛顿大学化学工程和机械工程的本科和研究生学位。

Test Efficiency of Panel Level Packaging

Kirk Pitta

Teradyne